1. Technical Field
The present invention relates to an AD conversion apparatus. In particular, the present invention relates to an asynchronous successive approximation AD conversion apparatus.
2. Related Art
An asynchronous successive approximation AD conversion apparatus is known as in, for example, Japanese Patent Application Publication No. 7-170185 (referred to hereinafter as “Patent Document 1”) and Shuo-Wei Mike Chen, Robert W. Brodersen, “A 6b 600 MS/s 5.3 mW Asynchronous ADC in 0.13 μm CMOS”, ISSCC 2006 DIGEST OF TECHNICAL PAPERS, Feb. 8, 2006, p. 574-575, p. 674 (referred to hereinafter as “Non-patent Document 1”). The asynchronous successive approximation AD conversion apparatus changes each bit without synchronizing the changing with a clock.
The asynchronous successive approximation AD conversion apparatus is provided with a completion detecting section that detects whether the comparison performed by the comparator is finished. The asynchronous successive approximation AD conversion apparatus moves on to the processing of the next bit cycle when the completion detecting section detects that the comparator has finished the comparison.
The asynchronous successive approximation AD conversion apparatus in Patent Document 1 is provided with an exclusive NOR gate and two inverter gates having different inverted potentials supplied by the potential difference between an input signal and a comparison signal, as described with reference to paragraph “0013” for example. The exclusive NOR gate outputs a comparison completion signal indicating that the comparison has been finished, when the output values of the two inverter gates are equal to each other.
The AD conversion apparatus disclosed in Non-patent Document 1 is provided with a comparator performing the differentiation operation, e.g. FIG. 31.5.3, and a NAND gate, e.g. the third paragraph of Non-patent Document 1. The NAND gate generates a ready signal indicating initiation of the subsequent bit cycle (paragraph 4) when the differential output signals Qn, Qp of the comparator shown in FIG. 31.5.3 are connected to the positive potential, in other words, when the reset is performed.
The AD conversion apparatus disclosed in Patent Document 1, however, must be provided with two specialized impedance gates serving as potential threshold values for the two different inverted potentials, such as a potential that is ¾ of the power supply potential and a potential that is ¼ of the power supply potential, and therefore the circuit size becomes undesirably large. Furthermore, since the AD conversion apparatus disclosed in Non-patent Document 1 must suspend processing from when the comparator outputs the conversion result to when the reset is preformed, the conversion time becomes undesirably long.
Cited documents:
Japanese Patent Application Publication No. 7-170185
Shuo-Wei Mike Chen, Robert W. Brodersen, “A 6b 600 MS/s 5.3 mW Asynchronous ADC in 0.13 μm CMOS”, ISSCC 2006 DIGEST OF TECHNICAL PAPERS, Feb. 8, 2006, p. 574-575, p. 674